Title: Design Verification Engineer
Location: San Francisco, CA - Santa Clara, CA
Design Verification
Qualifications: Bachelor's degree in computer science, Computer Engineering, or a related technical field
Required Experience/Skills
•8 to 10 years of hands-on experience with System Verilog/UVM methodology/Assertions/functional coverage •Proven track record of 'first-pass success' in ASIC development cycles.
•Experience in ARM Based SoC verification
•Experience with AXI/AHB/APB
•Proficiency with EDA tools and scripting languages (Python or TCL or Perl or Shell)
•Knowledge of C or C++ |
