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Position Details: Mask (Layout) Design Engineer
| Location: | San Jose, CA |
| Openings: | 1 |
| Salary Range: |
Title: Mask (Layout) Design Engineer
Location: San Jose CA
Key Skills: Cadence Virtuoso, analog/mixed-signal layout design
Required Experience/Skills:
- 7+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least
- 3+ years of recent experience on advance nodes including FinFET technologies
- Must be able to effectively switch between manufacturing nodes with minimal ramp.
- Great understanding of CAD flows and tools related to analog/mixed-signal layout design
- Excellent programming skills in languages: SKILL, Perl; Python is a plus
- Strong fundamentals in software development
- Solid experience with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
- Excellent communication and interpersonal skills
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