Position Details: Physical Design Engineer

Title: Physical Design Engineer

Location: Denver, CO

Required Experience/Skills
• 7+ years of hands-on experience in handling block/chip level implementation from RTL to GDSII
• Hands on experience in timing closure of blocks and full-chip
• Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
• Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc.
• Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such as Design Compiler, Fusion Compiler or Innovus.
• Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time
• Excellent scripting skills – TCL or Perl or Python
• Experience in Synthesis and Formal

Role and Responsibilities:
• Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs.

Synopsys/Cadence EDA tools (Preference: 5)
• Expertise in understanding constraints and fixing design/timing techniques
• Expertise in timing closure (STA) of high frequency blocks
• Experience performing detailed synthesis for blocks of high instance counts and complex designs – 1M+ instances and clock frequencies about 1 GHz
• Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
• Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
• Experience in Block-level and Full-chip integration.
• Proficient in Synopsys Fusion Compiler, Design Compiler, Cadence Innovus, PTSi
• Experience in Design Automation and UNIX system.
• Experience in Tcl/Tk, PERL, Python is a plus.
 

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